Smart card readers are currently used in devices intended to receive and/or transmit data, such as portable radiotelephones or television signal decoders. In such an application, the smart card contains data necessary for the operation of the device, for example, a code enabling to identify the user who has inserted the smart card into the reader, and the functions the device is authorized to carry out for this user. When a card is inserted into the reader, these two elements interact in two successive operating modes: in a first mode called initialization mode, the system is not yet operational. The reader is first to detect the presence of the smart card and then put the integrated circuit present on the surface of the smart card in its nominal operating conditions, that is to say, inter alia, supply a voltage thereto or initialize data paths so that the integrated circuit can communicate with the reader. In a second mode, called permanent mode, the integrated circuit is supplied with a voltage and receives a clock signal having the operational frequency, and the data paths are ready to transport data between the reader and the integrated circuit. During the initialization mode, the integrated circuit must receive a clock signal, having a frequency which may be different from the operational frequency. A signal having a frequency, called transition frequency, which is lower than the operational frequency, is preferably used which is lower than the operational frequency, which enables to reduce the energy consumption of the integrated circuit during the initialization mode. Such a choice is particularly advantageous in applications where the energy source used for supplying the integrated circuit with its supply voltage is a battery, as in portable radiotelephones. At the end of the initialization mode, the interface module is thus to switch the signal if provided to the clock terminal of the connector. This switching is realized by the switching device which, when it receives the order materialized by a certain value of the control signal, replaces the clock signal which formed the clock signal of the integrated circuit during the initialization mode, with the second clock signal intended to constitute the clock signal of the integrated circuit during the permanent mode.
The switching from one clock signal to another may in theory be carried out by means of a simple multiplexing controlled by the control signal. Such a multiplexing is asynchronous. If the first and second clock signals are in the inactive and the active state respectively, the moment when the clock signal orders the switching from the one to the other, said switching will cause the appearance of an unwanted active edge in the signal transmitted to the clock terminal, which unwanted edge will neither have been generated by the first nor by the second clock signal. Such an unwanted active edge may be harmful to the operation of the integrated circuit. To prevent this drawback, two authorization signals, each associated to one of the clock signals, may be generated and stored inside memory flip-flops, the clock signal selected by means of the control signal then only being transported to the clock terminal if its associated authorization signal is in the active state. The switching from one clock signal to the other is then to be effected in two periods: in a first period, the memory flip-flop in which the authorization signal associated to the first clock signal is stored is invalidated, that is to say, it receives an active signal on a reset-to-zero input, which thwarts the transport of the second clock signal to the clock terminal, after which, in a second period, the memory flip-flop in which the authorization signal associated to the second clock signal is stored is validated, that is to say, it receives an inactive signal on its reset-to-zero input which enables the transport of the second clock signal to the clock terminal. If such a mode of operation enables to prevent unwanted edges from occurring in the signal transmitted to the clock terminal, another disadvantage shows up, however. Because two steps are necessary for the invalidation of the flip-flop that is active before the switching, and for the validation of the flip-flop that must be active after the switching, a wanted active edge of the second clock signal, appearing immediately after the selection of said signal has been ordered by the control signal, may be ignored during the switching process, which may also be disadvantageous to the operation of the integrated circuit.
It is an object of the present invention to remedy the drawbacks described above by proposing a smart card reader in which the switching circuit is arranged so that the switching from one clock signal to the other takes place in a single step without, however, enabling unwanted active edges to occur in the signal transmitted to the clock terminal.